Highly reliable amorphous high-K gate oxide ZrO2

ABSTRACT

A gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO 2  gate oxides are provided. Also shown is a gate oxide with a conduction band offset in a range of approximately 5.16 eV to 7.8 eV. Gate oxides formed from elements such as zirconium are thermodynamically stable such that the gate oxides formed will have minimal reactions with a silicon substrate or other structures during any later high temperature processing stages. The process shown is performed at lower temperatures than the prior art, which further inhibits reactions with the silicon substrate or other structures. Using a thermal evaporation technique to deposit the layer to be oxidized, the underlying substrate surface smoothness is preserved, thus providing improved and more consistent electrical properties in the resulting gate oxide.

FIELD OF THE INVENTION

[0001] The invention relates to semiconductor devices and devicefabrication. Specifically, the invention relates to gate oxide layers oftransistor devices and their method of fabrication.

BACKGROUND OF THE INVENTION

[0002] In the semiconductor device industry, particularly in thefabrication of transistors, there is continuous pressure to reduce thesize of devices such as transistors. The ultimate goal is to fabricateincreasingly smaller and more reliable integrated circuits (ICs) for usein products such as processor chips, mobile telephones, or memorydevices such as DRAMs. The smaller devices are frequently powered bybatteries, where there is also pressure to reduce the size of thebatteries, and to extend the time between battery charges. This forcesthe industry to not only design smaller transistors, but to design themto operate reliably with lower power supplies.

[0003] A common configuration of a transistor is shown in FIG. 1. Whilethe following discussion uses FIG. 1 to illustrate a transistor from theprior art, one skilled in the art will recognize that the presentinvention could be incorporated into the transistor shown in FIG. 1 toform a novel transistor according to the invention. The transistor 100is fabricated in a substrate 110 that is typically silicon, but could befabricated from other semiconductor materials as well. The transistor100 has a first source/drain region 120 and a second source/drain region130. A body region 132 is located between the first source/drain regionand the second source/drain region, the body region 132 defining achannel of the transistor with a channel length 134. A gate dielectric,or gate oxide 140 is located on the body region 132 with a gate 150located over the gate oxide. Although the gate dielectric can be formedfrom materials other than oxides, the gate dielectric is typically anoxide, and is commonly referred to as a gate oxide. The gate may befabricated from polycrystalline silicon (polysilicon) or otherconducting materials such as metal may be used.

[0004] In fabricating transistors to be smaller in size and reliablyoperating on lower power supplies, one important design criteria is thegate oxide 140. A gate oxide 140, when operating in a transistor, hasboth a physical gate oxide thickness and an equivalent oxide thickness(EOT). The equivalent oxide thickness quantifies the electricalproperties, such as capacitance, of a gate oxide 140 in terms of arepresentative physical thickness. EOT is defined as the thickness of atheoretical SiO₂ layer that describes the actual electrical operatingcharacteristics of the gate oxide 140 in the transistor 100. Forexample, in traditional SiO₂ gate oxides, a physical oxide thickness maybe 5.0 nm, but due to undesirable electrical effects such as gatedepletion, the EOT may be 6.0 nm. A gate oxide other than SiO₂ may alsobe described electrically in terms of an EOT. In this case, thetheoretical oxide referred to in the EOT number is an equivalent SiO₂oxide layer. For example, SiO₂ has a dielectric constant ofapproximately 4. An alternate oxide with a dielectric constant of 20 anda physical thickness of 100 nm would have an EOT of approximately 20 nm(100*(4/20)), which represents a theoretical SiO₂ gate oxide.

[0005] Lower transistor operating voltages and smaller transistorsrequire thinner equivalent oxide thicknesses (EOTs). A problem with theincreasing pressure of smaller transistors and lower operating voltagesis that gate oxides fabricated from SiO₂ are at their limit with regardsto physical thickness and EOT. Attempts to fabricate SiO₂ gate oxidesthinner than today's physical thicknesses show that these gate oxides nolonger have acceptable electrical properties. As a result, the EOT of aSiO₂ gate oxide 140 can no longer be reduced by merely reducing thephysical gate oxide thickness.

[0006] Attempts to solve this problem have led to interest in gateoxides made from oxide materials other than SiO₂. Certain alternateoxides have a higher dielectric constant (k), which allows the physicalthickness of a gate oxide 140 to be the same as existing SiO₂ limits orthicker, but provides an EOT that is thinner than current SiO₂ limits.

[0007] A problem that arises in forming an alternate oxide layer on thebody region of a transistor is the process in which the alternate oxideis formed on the body region. Recent studies show that the surfaceroughness of the body region has a large effect on the electricalproperties of the gate oxide, and the resulting operatingcharacteristics of the transistor. The leakage current through aphysical 1.0 nm gate oxide increases by a factor of 10 for every 0.1increase in the root-mean-square (RMS) roughness. In forming analternate oxide layer on the body region of a transistor, a thin layerof the alternate material to be oxidized (typically a metal) must firstbe deposited on the body region. Current processes for depositing ametal or other alternate layer on the body region of a transistor areunacceptable due to their effect on the surface roughness of the bodyregion.

[0008]FIG. 2a shows a surface 210 of a body region 200 of a transistor.The surface 210 in the Figure has a high degree of smoothness, with asurface variation 220. FIG. 2b shows the body region 200 during aconventional sputtering deposition process stage. During sputtering,particles 230 of the material to be deposited bombard the surface 210 ata high energy. When a particle 230 hits the surface 210, some particlesadhere as shown by particle 235, and other particles cause damage asshown by pit 240. High energy impacts can throw off body regionparticles 215 to create the pits 240. A resulting layer 250 as depositedby sputtering is shown in FIG. 2c. The deposited layer/body regioninterface 255 is shown following a rough contour created by thesputtering damage. The surface of the deposited layer 260 also shows arough contour due to the rough interface 255.

[0009] In a typical process of forming an alternate material gate oxide,the deposited layer 250 is oxidized to convert the layer 250 to an oxidematerial. Existing oxidation processes do not, however, repair thesurface damage created by existing deposition methods such assputtering. As described above, surface roughness has a large influenceon the electrical properties of the gate oxide and the resultingtransistor.

[0010] What is needed is an alternate material gate oxide that is morereliable at existing EOTs than current gate oxides. What is also neededis an alternate material gate oxide with an EOT thinner thanconventional SiO₂. What is also needed is an alternative material gateoxide with a smooth interface between the gate oxide and the bodyregion. Because existing methods of deposition are not capable ofproviding a smooth interface with an alternate material gate oxide, whatis further needed is a method of forming an alternate material gateoxide that maintains a smooth interface.

[0011] Additionally, at higher process temperatures, any of severalmaterials used to fabricate the transistor, such as silicon, can reactwith other materials such as metals or oxygen to form unwanted silicidesor oxides. What is needed is a lower temperature process of forming gateoxides that prevents the formation of unwanted byproduct materials.

SUMMARY OF THE INVENTION

[0012] A method of forming a gate oxide on a surface such as atransistor body region is shown where a metal layer is deposited bythermal evaporation on the body region, the metal being chosen from agroup consisting of the group IVB elements of the periodic table. Themetal layer is then oxidized to convert the metal layer to a gate oxide.In one embodiment, the metal layer includes zirconium (Zr). Oneembodiment of the invention uses an electron beam source to evaporatethe metal layer onto the body region of the transistor. The oxidationprocess in one embodiment utilizes a krypton(Kr)/oxygen (O₂) mixedplasma process.

[0013] In addition to the novel process of forming a gate oxide layer, atransistor formed by the novel process exhibits novel features that mayonly be formed by the novel process. Thermal evaporation deposition of ametal layer onto a body region of a transistor preserves an originalsmooth surface roughness of the body region in contrast to other priordeposition methods that increase surface roughness. The resultingtransistor fabricated with the process of this invention will exhibit agate oxide/body region interface with a surface roughness variation aslow as 0.6 nm.

[0014] These and other embodiments, aspects, advantages, and features ofthe present invention will be set forth in part in the description whichfollows, and in part will become apparent to those skilled in the art byreference to the following description of the invention and referenceddrawings or by practice of the invention. The aspects, advantages, andfeatures of the invention are realized and attained by means of theinstrumentalities, procedures, and combinations particularly pointed outin the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015]FIG. 1 shows a common configuration of a transistor.

[0016]FIG. 2a shows a smooth surface of a body region of a transistor.

[0017]FIG. 2b shows a deposition process according to the prior art.

[0018]FIG. 2c shows a deposited film on a body region according to theprior art.

[0019]FIG. 3a shows a deposition process according to the invention.

[0020]FIG. 3b shows a magnified view of a deposited film on a bodyregion from FIG. 3a.

[0021]FIG. 4a shows a deposited film on a body region according to theinvention.

[0022]FIG. 4b shows a partially oxidized film on a body region accordingto the invention.

[0023]FIG. 4c shows a completely oxidized film on a body regionaccording to the invention.

[0024]FIG. 5 shows a perspective view of a personal computer.

[0025]FIG. 6 shows a schematic view of a central processing unit.

[0026]FIG. 7 shows a schematic view of a DRAM memory device.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] In the following detailed description of the invention, referenceis made to the accompanying drawings which form a part hereof, and inwhich is shown, by way of illustration, specific embodiments in whichthe invention may be practiced. In the drawings, like numerals describesubstantially similar components throughout the several views. Theseembodiments are described in sufficient detail to enable those skilledin the art to practice the invention. Other embodiments may be utilizedand structural, logical, and electrical changes may be made withoutdeparting from the scope of the present invention. The terms wafer andsubstrate used in the following description include any structure havingan exposed surface with which to form the integrated circuit (IC)structure of the invention. The term substrate is understood to includesemiconductor wafers. The term substrate is also used to refer tosemiconductor structures during processing, and may include other layersthat have been fabricated thereupon. Both wafer and substrate includedoped and undoped semiconductors, epitaxial semiconductor layerssupported by a base semiconductor or insulator, as well as othersemiconductor structures well known to one skilled in the art. The termconductor is understood to include semiconductors, and the terminsulator or dielectric is defined to include any material that is lesselectrically conductive than the materials referred to as conductors.

[0028] The term “horizontal” as used in this application is defined as aplane parallel to the conventional plane or surface of a wafer orsubstrate, regardless of the orientation of the wafer or substrate. Theterm “vertical” refers to a direction perpendicular to the horizonal asdefined above. Prepositions, such as “on”, “side” (as in “sidewall”),“higher”, “lower”, “over” and “under” are defined with respect to theconventional plane or surface being on the top surface of the wafer orsubstrate, regardless of the orientation of the wafer or substrate. Thefollowing detailed description is, therefore, not to be taken in alimiting sense, and the scope of the present invention is defined onlyby the appended claims, along with the full scope of equivalents towhich such claims are entitled.

[0029]FIG. 3a shows an electron beam evaporation technique to deposit amaterial on a surface such as a body region of a transistor. In FIG. 3a,a substrate 310 is placed inside a deposition chamber 300. The substratein this embodiment is masked by a first masking structure 312 and asecond masking structure 314. In this embodiment, the unmasked region316 includes a body region of a transistor, however one skilled in theart will recognize that other semiconductor device structures mayutilize this process. Also located within the deposition chamber 300 isan electron beam source 330, and a target material 334. Although in thisembodiment, an electron beam evaporation technique is used, it will beapparent to one skilled in the art that other thermal evaporationtechniques can be used without departing from the scope of theinvention. During the evaporation process, the electron beam source 330generates an electron beam 332. The electron beam hits the targetmaterial 334 and heats a portion of the target material enough to causethe surface of the target material to evaporate. The evaporated material336 is then distributed throughout the chamber 300, and the material 336deposits on surfaces that it contacts, such as the exposed body region316. The depositing material builds up to form a layer 320 of materialthat is chemically the same as the target material 334.

[0030] In one embodiment of the invention, the deposited material layer320 includes a pure metal layer chosen from the alkaline earth metals ingroup IVB of the periodic table. In one embodiment of the invention, thedeposited material layer 320 includes zirconium (Zr). In one embodimentof the invention, the target material is a 99.9999% pure slug ofzirconium. The choice of material is based on the properties of theoxide formed. Considerations included the thermodynamic stability of theoxide with silicon, the diffusion coefficient of the oxide at highprocessing temperatures such as 1000° K., the lattice match of the oxidewith silicon, the dielectric constant of the oxide, and the conductionband offset of the oxide. In one embodiment, the conduction band offsetof the metal oxide formed is in a range of approximately 5.16 eV to 7.8eV. In one embodiment, the deposited material layer 320 is substantiallyamorphous. A lower presence of grain boundaries in the substantiallyamorphous material layer 320 reduces the leakage current through thefinal gate oxide. Although the amorphous form is preferred, the materialchosen for oxidation, such as zirconium is also acceptable in itscrystalline form.

[0031] A thermal evaporation process such as the electron beamevaporation technique described above does not cause the surface damagethat is inherent in other deposition techniques such as the sputteringtechnique shown in FIG. 2b. This allows a very thin layer of material tobe deposited on a body region of a transistor, while maintaining asmooth interface. A thermal evaporation process such as the electronbeam evaporation technique described above also allows low processingtemperatures that inhibit the formation of unwanted byproducts such assuicides and oxides. In one embodiment, the thermal evaporation isperformed with a substrate temperature between approximately 150 and200° C.

[0032]FIG. 3b shows a magnified view of the body region 316 and thedeposited layer 320 from FIG. 3a. The interface 340 is shown with aroughness variation 346. The deposited layer surface 348 is also shownwith a similar surface roughness. One possible surface variation 346would be an atomic layer variation. In atomic smoothness, the greatestdifference in surface features is between a first atomic layer asindicated by layer 342 and a second atomic layer 344. The thermalevaporation deposition technique described above preserves atomicsmoothness such as is shown in FIG. 3b, however other acceptable levelsof surface roughness greater than atomic smoothness will also bereserved by the thermal evaporation technique.

[0033]FIGS. 4a-4 c show a low temperature oxidation process that is usedin one embodiment to convert the deposited layer 320 into a gate oxide.A deposited material layer 410 is shown in FIG. 4a on a substratesurface 400. The layer 410 forms an interface 420 with the substratesurface 400, and the layer 410 has an outer surface 430. The layer 410in this embodiment is deposited over a body region of a transistor,however the layer may be deposited on any surface within the scope ofthe invention.

[0034] In FIG. 4b, the layer 410 is in the process of being oxidized. Inone embodiment, the oxidation process includes a krypton/oxygen mixedplasma oxidation process. The mixed plasma process generates atomicoxygen or oxygen radicals in contrast to molecular oxygen or O₂ used inconventional thermal oxidation. The atomic oxygen is introduced to thelayer from all exposed directions as indicated by arrows 440, creatingan oxide portion 450. The atomic oxygen continues to react with thelayer and creates an oxidation interface 422. As the reactionprogresses, atomic oxygen diffuses through the oxide portion 450 andreacts at the oxidation interface 422 until the layer is completelyconverted to an oxide of the deposited material layer. FIG. 4c shows theresulting oxide layer 450 which spans a physical thickness 452 from theouter surface 430 to the interface 420.

[0035] In one embodiment, the processing variables for the mixed plasmaoxidation include a low ion bombardment energy of less than 7 eV, a highplasma density above 10¹²/cm³ and a low electron temperature below 1.3eV. In one embodiment, the substrate temperature is approximately 400°C. In one embodiment, a mixed gas of 3% oxygen with the balance beingkrypton at a pressure of 1 Torr is used. In one embodiment, a microwavepower density of 5 W/cm² is used. In one embodiment, the oxidationprocess provides a growth rate of 1.5 nm/min.

[0036] The low temperature mixed plasma oxidation process describedabove allows the deposited layer to be oxidized at a low temperature,which inhibits the formation of unwanted byproducts such as silicidesand oxides. The mixed plasma process in one embodiment is performed atapproximately 400° C. in contrast to prior thermal oxidation processesthat are performed at approximately 1000° C. The mixed plasma oxidationprocess has also been shown to provide improved thickness variation onsilicon (111) surfaces in addition to (100) surfaces. Although the lowtemperature mixed plasma process above describes the formation ofalternate material oxides, one skilled in the art will recognize thatthe process can also be used to form SiO₂ oxide structures.

[0037] Metals chosen from group IVB of the periodic table form oxidesthat are thermodynamically stable such that the gate oxides formed willhave minimal reactions with a silicon substrate or other structuresduring any later high temperature processing stages. Zirconium is oneexample of a metal selected from group IVB that forms athermodynamically stable gate oxide. In particular, zirconium forms anoxide comprised of ZrO₂. Zirconium oxide ZrO₂ exhibits a dielectricconstant of approximately 25, which allows for a thinner EOT thanconventional SiO₂. In addition to the stable thermodynamic propertiesinherent in the oxides chosen, the novel process used to form the oxidelayer is performed at lower temperatures than the prior art, whichfurther inhibits reactions with the silicon substrate or otherstructures.

[0038] A transistor made using the novel gate oxide process describedabove will possess several novel features. By creating an oxide materialwith a higher dielectric constant (k) and controlling surface roughnessduring formation, a gate oxide can be formed with an EOT thinner than 2nm. A thicker gate oxide that is more uniform, and easier to process canalso be formed with the alternate material oxide of the presentinvention, the alternate material gate oxide possessing an EOTequivalent to the current limits of SiO₂ gate oxides. The smooth surfaceof the body region is preserved during processing, and a resultingtransistor will have a smooth interface between the body region and thegate oxide with a surface roughness on the order of 0.6 nm.

[0039] Transistors created by the methods described above may beimplemented into memory devices and information handling devices asshown in FIGS. 5-7 and described below. While specific types of memorydevices and computing devices are shown below, it will be recognized byone skilled in the art that several types of memory devices andinformation handling devices could utilize the invention.

[0040] A personal computer, as shown in FIGS. 5 and 6, include a monitor500, keyboard input 502 and a central processing unit 504. The processorunit typically includes microprocessor 606, memory bus circuit 608having a plurality of memory slots 612(a-n), and other peripheralcircuitry 610. Peripheral circuitry 610 permits various peripheraldevices 624 to interface processor-memory bus 620 over input/output(I/O) bus 622. The personal computer shown in FIGS. 5 and 6 alsoincludes at least one transistor having a gate oxide according to theteachings of the present invention.

[0041] Microprocessor 606 produces control and address signals tocontrol the exchange of data between memory bus circuit 608 andmicroprocessor 606 and between memory bus circuit 608 and peripheralcircuitry 610. This exchange of data is accomplished over high speedmemory bus 620 and over high speed I/O bus 622.

[0042] Coupled to memory bus 620 are a plurality of memory slots612(a-n) which receive memory devices well known to those skilled in theart. For example, single inline memory modules (SIMMs) and dual in-linememory modules (DIMMs) may be used in the implementation of the presentinvention.

[0043] These memory devices can be produced in a variety of designswhich provide different methods of reading from and writing to thedynamic memory cells of memory slots 612. One such method is the pagemode operation. Page mode operations in a DRAM are defined by the methodof accessing a row of a memory cell arrays and randomly accessingdifferent columns of the array. Data stored at the row and columnintersection can be read and output while that column is accessed. Pagemode DRAMs require access steps which limit the communication speed ofmemory circuit 608. A typical communication speed for a DRAM deviceusing page mode is approximately 33 MHZ.

[0044] An alternate type of device is the extended data output (EDO)memory which allows data stored at a memory array address to beavailable as output after the addressed column has been closed. Thismemory can increase some communication speeds by allowing shorter accesssignals without reducing the time in which memory output data isavailable on memory bus 620. Other alternative types of devices includeSDRAM, DDR SDRAM, SLDRAM and Direct RDRAM as well as others such as SRAMor Flash memories.

[0045]FIG. 7 is a block diagram of an illustrative DRAM device 700compatible with memory slots 612(a-n). The description of DRAM 700 hasbeen simplified for purposes of illustrating a DRAM memory device and isnot intended to be a complete description of all the features of a DRAM.Those skilled in the art will recognize that a wide variety of memorydevices may be used in the implementation of the present invention. Theexample of a DRAM memory device shown in FIG. 7 includes at least onetransistor having a gate oxide according to the teachings of the presentinvention.

[0046] Control, address and data information provided over memory bus620 is further represented by individual inputs to DRAM 700, as shown inFIG. 7. These individual representations are illustrated by data lines702, address lines 704 and various discrete lines directed to controllogic 706.

[0047] As is well known in the art, DRAM 700 includes memory array 710which in turn comprises rows and columns of addressable memory cells.Each memory cell in a row is coupled to a common wordline. Additionally,each memory cell in a column is coupled to a common bitline. Each cellin memory array 710 includes a storage capacitor and an accesstransistor as is conventional in the art.

[0048] DRAM 700 interfaces with, for example, microprocessor 606 throughaddress lines 704 and data lines 702. Alternatively, DRAM 700 mayinterface with a DRAM controller, a micro-controller, a chip set orother electronic system. Microprocessor 606 also provides a number ofcontrol signals to DRAM 700, including but not limited to, row andcolumn address strobe signals RAS and CAS, write enable signal WE, anoutput enable signal OE and other conventional control signals.

[0049] Row address buffer 712 and row decoder 714 receive and decode rowaddresses from row address signals provided on address lines 704 bymicroprocessor 606. Each unique row address corresponds to a row ofcells in memory array 710. Row decoder 714 includes a wordline driver,an address decoder tree, and circuitry which translates a given rowaddress received from row address buffers 712 and selectively activatesthe appropriate wordline of memory array 710 via the wordline drivers.

[0050] Column address buffer 716 and column decoder 718 receive anddecode column address signals provided on address lines 704. Columndecoder 718 also determines when a column is defective and the addressof a replacement column. Column decoder 718 is coupled to senseamplifiers 720. Sense amplifiers 720 are coupled to complementary pairsof bitlines of memory array 710.

[0051] Sense amplifiers 720 are coupled to data-in buffer 722 anddata-out buffer 724. Data-in buffers 722 and data-out buffers 724 arecoupled to data lines 702. During a write operation, data lines 702provide data to data-in buffer 722. Sense amplifier 720 receives datafrom data-in buffer 722 and stores the data in memory array 710 as acharge on a capacitor of a cell at an address specified on address lines704.

[0052] During a read operation, DRAM 700 transfers data tomicroprocessor 606 from memory array 710. Complementary bitlines for theaccessed cell are equilibrated during a precharge operation to areference voltage provided by an equilibration circuit and a referencevoltage supply. The charge stored in the accessed cell is then sharedwith the associated bitlines. A sense amplifier of sense amplifiers 720detects and amplifies a difference in voltage between the complementarybitlines. The sense amplifier passes the amplified voltage to data-outbuffer 724.

[0053] Control logic 706 is used to control the many available functionsof DRAM 700. In addition, various control circuits and signals notdetailed herein initiate and synchronize DRAM 700 operation as known tothose skilled in the art. As stated above, the description of DRAM 700has been simplified for purposes of illustrating the present inventionand is not intended to be a complete description of all the features ofa DRAM. Those skilled in the art will recognize that a wide variety ofmemory devices, including but not limited to, SDRAMs, SLDRAMs, RDRAMsand other DRAMs and SRAMs, VRAMs and EEPROMs, may be used in theimplementation of the present invention. The DRAM implementationdescribed herein is illustrative only and not intended to be exclusiveor limiting.

Conclusion

[0054] Thus has been shown a gate oxide and method of fabricating a gateoxide that produce a more reliable and thinner equivalent oxidethickness. Gate oxides formed from elements in group IVB of the periodictable are thermodynamically stable such that the gate oxides formed willhave minimal reactions with a silicon substrate or other structuresduring any later high temperature processing stages. Zirconium oxide inparticular has been shown to provide excellent electrical andthermodynamic properties. In addition to the stable thermodynamicproperties inherent in the gate oxide of the invention, the processshown is performed at lower temperatures than the prior art, whichfurther inhibits reactions with the silicon substrate or otherstructures.

[0055] Transistors and higher level ICs or devices have been shownutilizing the novel gate oxide and process of formation. The higherdielectric constant (k) oxide materials shown in one embodiment areformed with an EOT thinner than 2 nm, e.g. thinner than possible withconventional SiO₂ gate oxides. A thicker gate oxide that is moreuniform, and easier to process has also been shown with at EOTequivalent to the current limits of SiO₂ gate oxides. In one embodimentof the present invention, the novel gate oxide provides a conductionband offset in a range of approximately 5.16 eV to 7.8 eV.

[0056] A novel process of forming a gate oxide has been shown where thesurface smoothness of the body region is preserved during processing,and the resulting transistor has a smooth interface between the bodyregion and the gate oxide with a surface roughness on the order of 0.6nm. This solves the prior art problem of poor electrical properties suchas high leakage current, created by unacceptable surface roughness.

[0057] Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat any arrangement which is calculated to achieve the same purpose maybe substituted for the specific embodiment shown. This application isintended to cover any adaptations or variations of the presentinvention. It is to be understood that the above description is intendedto be illustrative, and not restrictive. Combinations of the aboveembodiments, and other embodiments will be apparent to those of skill inthe art upon reviewing the above description. The scope of the inventionincludes any other applications in which the above structures andfabrication methods are used. The scope of the invention should bedetermined with reference to the appended claims, along with the fullscope of equivalents to which such claims are entitled.

What is claimed is:
 1. A method of forming a gate oxide on a transistorbody region, comprising: evaporation depositing a metal layer on thebody region, the metal being chosen from the group IVB elements of theperiodic table; and oxidizing the metal layer to form a metal oxidelayer on the body region.
 2. The method of claim 1, wherein evaporationdepositing the metal layer includes evaporation depositing a zirconiumlayer.
 3. The method of claim 1, wherein evaporation depositing themetal layer includes evaporation depositing by electron beamevaporation.
 4. The method of claim 3, wherein electron beam evaporationdepositing the metal layer includes electron beam evaporation of a99.9999% pure metal target material.
 5. The method of claim 1, whereinevaporation depositing the metal layer includes evaporation depositingat an approximate substrate temperature range of 150-400° C.
 6. Themethod of claim 1, wherein oxidizing the metal layer includes oxidizingat a temperature of approximately 400° C.
 7. The method of claim 1,wherein oxidizing the metal layer includes oxidizing with atomic oxygen.8. The method of claim 1, wherein oxidizing the metal layer includesoxidizing using a krypton (Kr)/oxygen (O₂) mixed plasma process.
 9. Amethod of forming a gate oxide on a transistor body region, comprising:evaporation depositing a metal layer on the body region, the metal beingchosen from the group IVB elements of the periodic table; and oxidizingthe metal layer using a krypton(Kr)/oxygen (O₂) mixed plasma process toform a metal oxide layer on the body region.
 10. The method of claim 9,wherein evaporation depositing the metal layer includes evaporationdepositing a zirconium layer.
 11. The method of claim 9, whereinevaporation depositing the metal layer includes evaporation depositingby electron beam evaporation.
 12. The method of claim 11, whereinelectron beam evaporation depositing the metal layer includes electronbeam evaporation of a 99.9999% pure metal target material.
 13. Themethod of claim 9, wherein evaporation depositing the metal layerincludes evaporation depositing at an approximate substrate temperaturerange of 150-400° C.
 14. A method of forming a transistor, comprising:forming first and second source/drain regions; forming a body regionbetween the first and second source/drain regions; evaporationdepositing a metal layer on the body region, the metal being chosen fromthe group IVB elements of the periodic table; oxidizing the metal layerto form a metal oxide layer on the body region; and coupling a gate tothe metal oxide layer.
 15. The method of claim 14, wherein evaporationdepositing the metal layer includes evaporation depositing a zirconiumlayer.
 16. The method of claim 14, wherein evaporation depositing themetal layer includes evaporation depositing by electron beamevaporation.
 17. The method of claim 16, wherein electron beamevaporation depositing the metal layer includes electron beamevaporation of a 99.9999% pure metal target material.
 18. The method ofclaim 14, wherein evaporation depositing the metal layer includesevaporation depositing at an approximate substrate temperature range of150-400° C.
 19. The method of claim 14, wherein oxidizing the metallayer includes oxidizing at a temperature of approximately 400° C. 20.The method of claim 14, wherein oxidizing the metal layer includesoxidizing with atomic oxygen.
 21. The method of claim 14, whereinoxidizing the metal layer includes oxidizing using a krypton (Kr)/oxygen(O₂) mixed plasma process.
 22. A method of forming a memory array,comprising: forming a number of access transistors, comprising: formingfirst and second source/drain regions; forming a body region between thefirst and second source/drain regions; evaporation depositing a metallayer on the body region, the metal being chosen from the group IVBelements of the periodic table; oxidizing the metal layer to form ametal oxide layer on the body region; coupling a gate to the metal oxidelayer; forming a number of wordlines coupled to a number of the gates ofthe number of access transistors; forming a number of sourcelinescoupled to a number of the first source/drain regions of the number ofaccess transistors; and forming a number of bitlines coupled to a numberof the second source/drain regions of the number of access transistors.23. The method of claim 22, wherein evaporation depositing the metallayer includes evaporation depositing a zirconium layer.
 24. The methodof claim 22, wherein evaporation depositing the metal layer includesevaporation depositing by electron beam evaporation.
 25. The method ofclaim 24, wherein electron beam evaporation depositing the metal layerincludes electron beam evaporation of a 99.9999% pure metal targetmaterial.
 26. The method of claim 22, wherein evaporation depositing themetal layer includes evaporation depositing at an approximate substratetemperature range of 150-400° C.
 27. The method of claim 22, whereinoxidizing the metal layer includes oxidizing at a temperature ofapproximately 400° C.
 28. The method of claim 22, wherein oxidizing themetal layer includes oxidizing with atomic oxygen.
 29. The method ofclaim 22, wherein oxidizing the metal layer includes oxidizing using akrypton (Kr)/oxygen (O₂) mixed plasma process.
 30. A method of formingan information handling system, comprising: forming a processor; forminga memory array, comprising: forming a number of access transistors,comprising: forming first and second source/drain regions; forming abody region between the first and second source/drain regions;evaporation depositing a metal layer on the body region, the metal beingchosen from the group IVB elements of the periodic table; oxidizing themetal layer to form a metal oxide layer on the body region; coupling agate to the metal oxide layer; forming a number of wordlines coupled toa number of the gates of the number of access transistors; forming anumber of sourcelines coupled to a number of the first source/drainregions of the number of access transistors; forming a number ofbitlines coupled to a number of the second source/drain regions of thenumber of access transistors; and forming a system bus that couples theprocessor to the memory array.
 31. The method of claim 30, whereinevaporation depositing the metal layer includes evaporation depositing azirconium layer.
 32. The method of claim 30, wherein evaporationdepositing the metal layer includes evaporation depositing by electronbeam evaporation.
 33. The method of claim 32, wherein electron beamevaporation depositing the metal layer includes electron beamevaporation of a 99.9999% pure metal target material.
 34. The method ofclaim 30, wherein evaporation depositing the metal layer includesevaporation depositing at an approximate substrate temperature range of150-400° C.
 35. The method of claim 30, wherein oxidizing the metallayer includes oxidizing at a temperature of approximately 400° C. 36.The method of claim 30, wherein oxidizing the metal layer includesoxidizing with atomic oxygen.
 37. The method of claim 30, whereinoxidizing the metal layer includes oxidizing using a krypton (Kr)/oxygen(O₂) mixed plasma process.
 38. A transistor, comprising: a first andsecond source/drain region; a body region located between the first andsecond source/drain regions, wherein a surface portion of the bodyregion has a surface roughness of approximately 0.6 nm; a zirconiumoxide dielectric layer coupled to the surface portion of the bodyregion; and a gate coupled to the zirconium oxide dielectric layer. 39.The transistor of claim 38, wherein the zirconium oxide dielectric layerincludes ZrO₂.
 40. The transistor of claim 38, wherein the surfaceportion of the body region is oriented in the (100) crystalline plane.41. The transistor of claim 38, wherein the surface portion of the bodyregion is oriented in the (111) crystalline plane.
 42. The transistor ofclaim 38, wherein the zirconium oxide dielectric layer is substantiallyamorphous.
 43. A memory array, comprising: a number of accesstransistors, comprising: a first and second source/drain region; a bodyregion located between the first and second source/drain regions,wherein a surface portion of the body region has a surface roughness ofapproximately 0.6 nm; a zirconium oxide dielectric layer coupled to thesurface portion of the body region; a gate coupled to the zirconiumoxide dielectric layer; a number of wordlines coupled to a number of thegates of the number of access transistors; a number of sourcelinescoupled to a number of the first source/drain regions of the number ofaccess transistors; and a number of bitlines coupled to a number of thesecond source/drain regions of the number of access transistors.
 44. Thememory array of claim 43, wherein the zirconium oxide dielectric layerincludes ZrO₂.
 45. The memory array of claim 43, wherein the zirconiumoxide dielectric layer exhibits a dielectric constant (k) ofapproximately
 25. 46. The memory array of claim 43, wherein thezirconium oxide dielectric layer is substantially amorphous.
 47. Aninformation handling device, comprising: a processor; a memory array,comprising: a number of access transistors, comprising: a first andsecond source/drain region; a body region located between the first andsecond source/drain regions, wherein a surface portion of the bodyregion has a surface roughness of approximately 0.6 nm; a zirconiumoxide dielectric layer coupled to the surface portion of the bodyregion; a gate coupled to the zirconium oxide dielectric layer; a numberof wordlines coupled to a number of the gates of the number of accesstransistors; a number of sourcelines coupled to a number of the firstsource/drain regions of the number of access transistors; a number ofbitlines coupled to a number of the second source/drain regions of thenumber of access transistors; and a system bus coupling the processor tothe memory device.
 48. The information handling device of claim 47,wherein the zirconium oxide dielectric layer includes ZrO₂.
 49. Theinformation handling device of claim 47, wherein the zirconium oxidedielectric layer exhibits a dielectric constant (k) of approximately 25.50. The information handling device of claim 47, wherein the zirconiumoxide dielectric layer is substantially amorphous.
 51. A transistorformed by the process, comprising: forming a body region coupled betweena first source/drain region and a second source/drain region;evaporation depositing a metal layer on the body region, the metal beingchosen from the group IVB elements of the periodic table; oxidizing themetal layer to form a metal oxide layer on the body region; and couplinga gate to the metal oxide layer.
 52. The transistor of claim 51, whereinevaporation depositing the metal layer includes evaporation depositing azirconium layer.
 53. The transistor of claim 51, wherein evaporationdepositing the metal layer includes evaporation depositing by electronbeam evaporation.
 54. The method of claim 51, wherein oxidizing themetal layer includes oxidizing using a krypton (Kr)/oxygen (O₂) mixedplasma process.
 55. A method of forming a gate oxide on a transistorbody region, comprising: electron beam evaporation depositing a metallayer on the body region, the metal being chosen from the group IVBelements of the periodic table; and oxidizing the metal layer to form ametal oxide layer on the body region.
 56. The method of claim 55,wherein oxidizing the metal layer includes oxidizing a metal layer toform an oxide with a conduction band offset in a range of approximately5.16 eV to 7.8 eV.
 57. A transistor, comprising: a first and secondsource/drain region; a body region located between the first and secondsource/drain regions, wherein a surface portion of the body region has asurface roughness of approximately 0.6 nm; a group IVB oxide dielectriclayer coupled to the surface portion of the body region, wherein theoxide dielectric layer has a conduction band offset in a range ofapproximately 5.16 eV to 7.8 eV; and a gate coupled to the group IVBoxide dielectric layer.
 58. The transistor of claim 57, wherein thezirconium oxide dielectric layer includes ZrO₂.
 59. The transistor ofclaim 57, wherein the surface portion of the body region is oriented inthe (100) crystalline plane.
 60. The transistor of claim 57, wherein thesurface portion of the body region is oriented in the (111) crystallineplane.
 61. The transistor of claim 57, wherein the zirconium oxidedielectric layer is substantially amorphous.